I'm writing SystemVerilog code and I notice that $sformat is a system task, not a function. Is there a function equivalent to $sformat?
I'd like to do the following inside a function:
assert(my_dto_h.a == 10) else begin
`ovm_error("component", $sformat("my_dto_h.a should be 10, not %0d", my_dto_h.a))
end
Unfortunately, I'm getting the the following run-time error from QuestaSim 10.2:
** Error: (vsim-PLI-3029) component.sv(105): Expected a system function, not system task '$sformat'.
2 Answers
Yes, $sformatf
From the LRM:
The system function
$sformatfbehaves like$sformatexcept that the string result is passed back as the function result value for$sformatf, not placed in the first argument as for$sformat. Thus$sformatfcan be used where a string value would be valid.
variable_format_string_output_function ::=
$sformatf ( format_string [ , list_of_arguments ] )
Example:
string s;
s = $sformatf("Value = %0d", value);
You can use $psprintf. It is not part of the standard, but many simulators such as QuestaSim and VCS support it.
assert(my_dto_h.a == 10) else begin
`ovm_error("component", $psprintf("my_dto_h.a should be 10, not %0d", my_dto_h.a))
end
