(System)Verilog Macro Containing a Comment?

(System)Verilog Macro Containing a Comment?

Is there any way in verilog to write a macro containing a comment so the comment will be 'instantiated' in every instance of the macro? I need the comment inside the macro to turn off a lint complaint about the other code in the macro.

3 Answers

The use of comments pragmas for tools is discouraged. The (System)Verilog LRM is not very clear about the use of comments in macro processing. It is clear that single line comments (preceded with // are not part of the expanded text, but makes no mention about /* mult-line */ comments. Most pre-processors remove all comments before expandint text.

Verilog-2001 added attributes (* text *) to the language, but people are still not aware that they should be using them instead of comments.

You should use block comments (/* */) and probable multi-line macros. Example:

`define macro_with_comment \
  /* your comment here */ \
  macro_body_here \
  /* another your comment here */ \
  another_line

Be warned, macros are a pain to debug is something goes wrong.

0

You can try to use the following syntax that worked for me with a similar issue:

`define macro_with_comment(SLASH_CHAR=/) \
    ``SLASH_CHAR``SLASH_CHAR <write your comment here> \
     macro body here \
    ``SLASH_CHAR``SLASH_CHAR <write your comment here> \
     macro body here...
2

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Marcus Vance
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Marcus Vance

Marcus Vance is a cybersecurity auditor and technology writer dedicated to educating the public about online safety, data privacy regulations, enterprise security, and emerging cyber threats.