Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation, by removing the clock signal when the circuit is not in use. Clock gating saves power by pruning the clock tree, at the cost of adding more logic to a circuit.

What is clock gating in physical design?

Clock Gating is defined as: “Clock gating is a technique/methodology to turn off the clock to certain parts of the digital design when not needed”.

What are clock gating cells?

A clock gating check occurs when a gating signal can control the path of a clock signal at a logic cell. ... Logic cell where clock gating occurs is also referred to as gating cell. One condition for a clock gating check is that clock that goes through cell must be used as a clock downstream.