At-speed scan test involves loading scan chains at a slow clock rate and then applying two clock pulses at the functional frequency. If the circuit is operational, then the transition will propagate to the end of the path in time and the correct value will be captured.

What is speed fault?

At-speed fault models

If the captured response indicates that the logic involved did not transition as expected during the cycle time, the path fails the test and is considered to contain a defect.

What is DFT and ATPG?

Automatic Test Pattern Generation, or ATPG, is a process used in semiconductor electronic device testing wherein the test patterns required to check a device for faults are automatically generated by a program. ...