A similar function can be done by an OR gate, with the signal being forced high or let through. So gating a clock means forcing it low/high or letting it pass through. ... These include metastability when taking clocked signals into the gated clock domain and worse results from timing-driven synthesis/layout.

What is the advantage of clock gating?

Clock gating saves power by pruning the clock tree, at the cost of adding more logic to a circuit. Pruning the clock disables portions of the circuitry so that the flip-flops in them do not have to switch states.

Does clock gating reduce static power?

Power dissipation has a dynamic component, due to the switching of active devices, and a static component, due to the leakage of inactive devices. ... A promising technique to reduce the power dissipation of the clock net is selectively stopping the clock in parts of the circuit, called “clock gating”.